1. Field of the Invention
Embodiments of the present invention relate generally to a method of manufacturing a gate structure and a method of manufacturing a semiconductor device including the same. More particularly, embodiments of the invention relate to a method of manufacturing a gate structure using a surface treatment involving a solution comprising ozone, and a method of manufacturing a semiconductor device including the same.
A claim of priority is made to Korean Patent Application No. 2005-0066674, filed on Jul. 22, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Semiconductor memory devices can be broadly classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. Volatile memory devices lose stored data when disconnected from a power source, while non-volatile memory devices maintain stored data when disconnected from power. Examples of volatile semiconductor memory devices include static random access memory (SRAM) devices and dynamic random access memory (DRAM) devices, and examples of non-volatile semiconductor memory devices include erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory.
There is a continuing trend for semiconductor devices to become increasingly integrated, and for their design rule to decrease. With this trend, semiconductor devices have had to undergo a variety of changes. For example, when forming a DRAM device having a storage capacity of a gigabyte, a lower operating power and a finer line width are required. Thus, in a DRAM cell, a gate conductive layer of a transistor has a thickness less than about 100 Å. In order to form the thin gate conductive layer uniformly and stably, a gate oxide layer under the gate conductive layer must be treated properly.
Similarly, a memory cell of a non-volatile semiconductor memory device, as a line width of a gate structure is reduced, the thickness of a floating gate in the gate structure is reduced. For example, where the line width of the gate structure is about 90 nm, the thickness of the floating gate is about 8 nm; where the line width is about 65 nm, the thickness is about 6 nm; and where the line width is about 45 nm, the thickness is about 3 nm. However, where the thickness of the floating gate becomes less than about 6 nm, a leakage current of the floating gate may increase beyond a permissible range. In other words, as the thickness of the floating gate drops below a critical level, it becomes increasingly difficult to maintain stored charge therein. As a result, the non-volatile semiconductor memory device may not operate properly.
As non-volatile semiconductor memory devices become increasingly integrated, a corresponding reduction in the size of a floating gate within each memory cell of the devices tends to reduce the capacitance between the control gate and floating gate of the memory cell. In order to improve the operating efficiency of the non-volatile semiconductor memory device at a low voltage, a coupling ratio of the dielectric layer must be increased. One way to increase the coupling ratio of the dielectric layer is to form a U-shaped floating gate. Another method is to form the floating gate with a thickness less than about 100 Å.
As an alternative method, a method of forming the floating gate using a nano-crystalline material rather than polysilicon has been studied.
In non-volatile semiconductor memory devices using the nano-crystalline material to form the floating gate, charges may be trapped in the nano-crystalline particles so that some inferior nano-crystalline particles do not have influence on storing the charge. Thus, the leakage current is reduced relative to non-volatile semiconductor memory device including the floating gate formed using polysilicon. One main material that has been studied as the nano-crystalline material is, for example, nano-crystalline silicon.
A nano-crystalline silicon layer is usually formed by chemical vapor deposition (CVD). Where the nano-crystalline silicon layer does not have nano-particles having proper size, uniform distribution and enough density, the charge stored in the nano-crystalline silicon layer is reduced. Hence, in the CVD process for forming the nano-crystalline silicon layer, it is very difficult to deposit silicon having proper size, uniform distribution and sufficient density.
As mentioned above, forming the thin gate conductive layer stably is important in the DRAM device having a fine design rule. Additionally, for forming the non-volatile semiconductor memory device having improved properties, it is important to form the polysilicon layer or the nano-crystalline silicon layer with relatively uniform thickness and roughness.
For that purpose, the surface of the silicon oxide layer is often treated with solution including hydrogen fluoride (HF) or solution including sulphuric acid (H2SO4) and hydrogen peroxide (H2O2). After the surface treatment, the CVD process is performed by introducing source gas having silicon, such as SiH4, etc. By the surface treatment for the silicon oxide layer, silanol (SiOH) is formed on the surface of the silicon oxide layer. Then, silanol promotes a decomposition of silane so that a deposition rate of silane is increased.
However, when silanol is formed using the hydrogen fluoride solution, the silicon oxide layer is etched by the hydrogen fluoride solution so that the thickness of the silicon oxide layer is changed. In addition, when the silicon oxide layer is treated by the sulphuric acid solution and hydrogen peroxide solution, environment pollution occurs and the cost increases.